Altos Design Automation's Complex I/O Characterization and IP Validation Tools Being Utilized by ON Semiconductor

Online, February 1, 2011 (Newswire.com) - CAMPBELL, Calif. - Altos Design Automation Inc. today announced that ON Semiconductor (Nasdaq: ONNN), a premier supplier of high performance silicon solutions for energy efficient electronics, has adopted Altos' Liberate ultra-fast cell characterizer and the Liberate LV library validation solution for use with its product design and development.

"ON Semiconductor is utilizing Liberate to characterize complex high-speed I/O (interface) cells including those that are primarily analog, such as CML (Current Mode Logic), and those with high node-per-pad pin counts, such as SSTL (Stub Series Terminated Logic)," said David Kelly, senior director of Intellectual Property (IP) Development at ON Semiconductor. We are also implementing Liberate LV to ensure the accuracy of internally generated libraries and to validate libraries we receive from third party suppliers. We have been extremely pleased with the speed and ease-of-use we've experienced with Liberate and Liberate LV, in particular for characterization of our most challenging cells."

Jim McCanny, Altos CEO and founder, said, "Design reuse has become essential to productive chip design. By using Liberate to characterize their complex I/O cells, ON Semiconductor is able to quickly migrate to new process nodes so that they can take advantage of growing opportunities in automotive, aerospace and industrial applications."

About Liberate
Liberate is an ultra-fast library creator that generates electrical models in Liberty®, Verilog, Vital and IBIS formats. Liberate supports all the latest models for timing, noise and power such as CCS (Composite Current Source) and ECSM (Effective Current Source Models) Liberate also supports ultra low power and high speed design styles that include power gating cells, state retention registers, level shifters, pulse clocking and CML.

About Liberate LV
Liberate LV is an independent and comprehensive solution to validating and qualifying library views. This includes checking all functional, timing, noise, and power data for potential problems before wide-spread use by multiple design teams.

Liberate LV performs a number of necessary library validation steps including ensuring functional consistency between the transistor level sub-circuits and the Liberty® and Verilog files; accuracy validation of electrical analysis tools analysis versus SPICE circuit simulation and library version comparison. It is able to correlate both current source modeling delays and NLDM delays against actual spice simulation results. These results are available in text reports, HTML files, graphical plots and/or readable in spreadsheet applications. Liberate LV supports a variety of commercially available circuit and logic simulators and numerous sign-off analysis tools.

About Altos
Altos Design Automation provides ultra-fast, fully-automated characterization technology for the creation of library views for timing, signal integrity and power analysis and optimization. Altos advanced modeling solutions are used by both corner-based and statistical-based design implementation flows to reduce time to market and improve yield.

Privately held, Altos was founded in 2005 in Santa Clara, CA. Its corporate headquarters is at 1919 South Bascom Ave., Suite 250, Campbell, CA 95008. Telephone: (408) 980-8056. On the Web at: http://www.altos-da.com/