"Constraining Designs for Synthesis and Timing Analysis" by Sridhar Gangadharan and Sanjay Churiwala now available.

Atrenta announced today the addition of an interview program at DAC 2012. At the Atrenta Booth (2230) customers, partners and investors such as Jim Hogan will comment on how Atrenta's SpyGlass® RTL analysis platform helps their business.

ICScape, after enabling over 100 successful customer tapeouts, is now ready to market its solutions worldwide. The expansion is driven by US$28 million in financial backing the company received in 2011, mostly from China Electronics Corporation (CEC)

Atrenta announced today the availability of release 4.7 of its SpyGlass® RTL analysis and optimization platform, which includes significant performance, optimization and usability enhancements plus new features.

Atrenta has created a European technical advisory board (TAB). This group expands the existing Atrenta advisory board, which is composed of high-profile researchers and professors in the US and Asia.

Ten intellectual property (IP) providers have qualified their soft IP for inclusion in the TSMC 9000 IP library using the Atrenta IP Handoff Kit.

Dorado, Inc. has announced that TSMC is using Dorado's TweakerTM ECO (Engineering Change Order) Platform for incremental optimization in TSMC's Integrated Signoff Flow (ISF).

Atrenta and imec have jointly developed an advanced planning and partitioning design flow for heterogeneous 3D stacked ICs and will be demonstrating this flow at DAC in San Diego from June 6 - 8, 2011 at the Atrenta booth (1643).