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Press Release
May 27, 2013
Atrenta Announces a New Text Book on Timing Constraints
"Constraining Designs for Synthesis and Timing Analysis" by Sridhar Gangadharan and Sanjay Churiwala now available.
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Press Release
Jun 1, 2012
Atrenta Probes SpyGlass® Value At DAC - Customers, Partners And Investors To Comment On SpyGlass Impact
Atrenta announced today the addition of an interview program at DAC 2012. At the Atrenta Booth (2230) customers, partners and investors such as Jim Hogan will comment on how Atrenta's SpyGlass® RTL analysis platform helps their business.
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Press Release
May 14, 2012
ICScape™ Grows Globally - Design Closure Startup with Over 100 Tapeouts Gets $28M in Funding
ICScape, after enabling over 100 successful customer tapeouts, is now ready to market its solutions worldwide. The expansion is driven by US$28 million in financial backing the company received in 2011, mostly from China Electronics Corporation (CEC)
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Press Release
May 1, 2012
Atrenta Ships 4.7 Release of SpyGlass® Platform
Atrenta announced today the availability of release 4.7 of its SpyGlass® RTL analysis and optimization platform, which includes significant performance, optimization and usability enhancements plus new features.
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Press Release
Apr 24, 2012
Atrenta Expands Technical Advisory Board in Europe
Atrenta has created a European technical advisory board (TAB). This group expands the existing Atrenta advisory board, which is composed of high-profile researchers and professors in the US and Asia.
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Press Release
Mar 7, 2012
Atrenta and TSMC IP Quality Initiative Gains Broad Industry Acceptance
Ten intellectual property (IP) providers have qualified their soft IP for inclusion in the TSMC 9000 IP library using the Atrenta IP Handoff Kit.
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Press Release
Jun 5, 2011
Dorado Tweaker ECO Platform In Use At TSMC For Integrated Signoff Flow
Dorado, Inc. has announced that TSMC is using Dorado's TweakerTM ECO (Engineering Change Order) Platform for incremental optimization in TSMC's Integrated Signoff Flow (ISF).
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Press Release
May 24, 2011
Imec and Atrenta Develop Exploration Flows for 3D ICs
Atrenta and imec have jointly developed an advanced planning and partitioning design flow for heterogeneous 3D stacked ICs and will be demonstrating this flow at DAC in San Diego from June 6 - 8, 2011 at the Atrenta booth (1643).
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